5.1 Designing Register Machines
- 5.1.1 A Language for Describing Register Machines
- 5.1.2 Abstraction in Machine Design
- 5.1.3 Subroutines
- 5.1.4 Using a Stack to Implement Recursion
- 5.1.5 Instruction Summary
5.2 A Register-Machine Simulator
- 5.2.1 The Machine Model
- 5.2.2 The Assembler
- 5.2.3 Generating Execution Procedures for Instructions
- 5.2.4 Monitoring Machine Performance
5.3 Storage Allocation and Garbage Collection
- 5.3.1 Memory as Vectors
- 5.3.2 Maintaining the Illusion of Infinite Memory
5.4 The Explicit-Control Evaluator
- 5.4.1 The Core of the Explicit-Control Evaluator
- 5.4.2 Sequence Evaluation and Tail Recursion
- 5.4.3 Conditionals, Assignments, and Definitions
- 5.4.4 Running the Evaluator
5.5 Compilation
- 5.5.1 Structure of the Compiler
- 5.5.2 Compiling Expressions
- 5.5.3 Compiling Combinations
- 5.5.4 Combining Instruction Sequences
- 5.5.5 An Example of Compiled Code
- 5.5.6 Lexical Addressing
- 5.5.7 Interfacing Compiled Code to the Evaluator

5 Computing with Register Machines⁠

Contents